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# Created by write_sdc on Mon Jun 17 07:32:17 2019

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set sdc_version 2.0

set_units -time ns
set_max_fanout 10 [current_design]
set_max_transition 0.1 [current_design]
set_logic_zero [get_ports {rocc_resp_data_i[data][63]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][62]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][61]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][60]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][59]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][58]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][57]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][56]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][55]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][54]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][53]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][52]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][51]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][50]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][49]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][48]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][47]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][46]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][45]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][44]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][43]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][42]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][41]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][40]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][39]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][38]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][37]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][36]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][35]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][34]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][33]}]
set_logic_zero [get_ports {rocc_resp_data_i[data][32]}]
set_logic_zero [get_ports {rocc_ctrl_i[interrupt]}]
set_load -pin_load 3 [get_ports rocc_cmd_v_o]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_funct][6]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_funct][5]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_funct][4]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_funct][3]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_funct][2]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_funct][1]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_funct][0]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_rs2][4]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_rs2][3]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_rs2][2]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_rs2][1]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_rs2][0]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_rs1][4]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_rs1][3]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_rs1][2]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_rs1][1]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_rs1][0]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_xd]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_xs1]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_xs2]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_rd][4]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_rd][3]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_rd][2]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_rd][1]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_rd][0]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_opcode][6]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_opcode][5]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_opcode][4]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_opcode][3]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_opcode][2]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_opcode][1]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[inst_opcode][0]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][63]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][62]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][61]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][60]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][59]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][58]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][57]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][56]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][55]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][54]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][53]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][52]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][51]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][50]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][49]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][48]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][47]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][46]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][45]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][44]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][43]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][42]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][41]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][40]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][39]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][38]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][37]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][36]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][35]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][34]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][33]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][32]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][31]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][30]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][29]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][28]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][27]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][26]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][25]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][24]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][23]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][22]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][21]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][20]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][19]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][18]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][17]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][16]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][15]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][14]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][13]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][12]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][11]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][10]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][9]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][8]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][7]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][6]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][5]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][4]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][3]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][2]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][1]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs1][0]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][63]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][62]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][61]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][60]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][59]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][58]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][57]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][56]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][55]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][54]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][53]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][52]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][51]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][50]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][49]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][48]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][47]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][46]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][45]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][44]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][43]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][42]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][41]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][40]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][39]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][38]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][37]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][36]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][35]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][34]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][33]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][32]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][31]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][30]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][29]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][28]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][27]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][26]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][25]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][24]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][23]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][22]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][21]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][20]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][19]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][18]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][17]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][16]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][15]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][14]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][13]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][12]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][11]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][10]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][9]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][8]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][7]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][6]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][5]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][4]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][3]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][2]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][1]}]
set_load -pin_load 3 [get_ports {rocc_cmd_data_o[rs2][0]}]
set_load -pin_load 3 [get_ports rocc_resp_ready_o]
set_load -pin_load 3 [get_ports rocc_mem_req_ready_o]
set_load -pin_load 3 [get_ports rocc_mem_resp_v_o]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][39]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][38]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][37]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][36]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][35]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][34]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][33]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][32]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][31]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][30]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][29]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][28]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][27]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][26]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][25]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][24]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][23]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][22]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][21]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][20]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][19]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][18]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][17]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][16]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][15]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][14]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][13]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][12]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][11]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][10]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][9]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][8]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][7]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][6]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][5]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][4]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][3]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][2]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][1]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[addr][0]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[tag][9]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[tag][8]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[tag][7]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[tag][6]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[tag][5]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[tag][4]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[tag][3]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[tag][2]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[tag][1]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[tag][0]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[cmd][4]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[cmd][3]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[cmd][2]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[cmd][1]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[cmd][0]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[typ][2]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[typ][1]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[typ][0]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][63]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][62]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][61]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][60]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][59]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][58]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][57]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][56]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][55]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][54]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][53]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][52]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][51]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][50]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][49]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][48]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][47]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][46]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][45]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][44]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][43]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][42]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][41]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][40]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][39]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][38]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][37]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][36]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][35]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][34]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][33]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][32]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][31]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][30]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][29]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][28]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][27]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][26]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][25]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][24]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][23]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][22]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][21]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][20]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][19]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][18]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][17]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][16]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][15]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][14]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][13]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][12]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][11]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][10]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][9]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][8]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][7]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][6]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][5]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][4]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][3]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][2]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][1]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data][0]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[nack]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[replay]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[has_data]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][63]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][62]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][61]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][60]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][59]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][58]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][57]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][56]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][55]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][54]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][53]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][52]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][51]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][50]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][49]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][48]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][47]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][46]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][45]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][44]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][43]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][42]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][41]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][40]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][39]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][38]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][37]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][36]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][35]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][34]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][33]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][32]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][31]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][30]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][29]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][28]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][27]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][26]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][25]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][24]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][23]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][22]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][21]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][20]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][19]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][18]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][17]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][16]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][15]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][14]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][13]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][12]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][11]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][10]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][9]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][8]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][7]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][6]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][5]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][4]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][3]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][2]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][1]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[data_word_bypass][0]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][63]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][62]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][61]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][60]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][59]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][58]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][57]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][56]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][55]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][54]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][53]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][52]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][51]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][50]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][49]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][48]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][47]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][46]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][45]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][44]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][43]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][42]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][41]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][40]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][39]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][38]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][37]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][36]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][35]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][34]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][33]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][32]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][31]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][30]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][29]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][28]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][27]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][26]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][25]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][24]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][23]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][22]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][21]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][20]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][19]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][18]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][17]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][16]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][15]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][14]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][13]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][12]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][11]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][10]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][9]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][8]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][7]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][6]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][5]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][4]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][3]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][2]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][1]}]
set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o[store_data][0]}]
set_load -pin_load 3 [get_ports {rocc_ctrl_o[s]}]
set_load -pin_load 3 [get_ports {rocc_ctrl_o[exception]}]
set_load -pin_load 3 [get_ports {rocc_ctrl_o[host_id]}]
set_load -pin_load 3 [get_ports fsb_node_ready_o]
set_load -pin_load 3 [get_ports fsb_node_v_o]
set_load -pin_load 3 [get_ports {fsb_node_data_o[destid][3]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[destid][2]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[destid][1]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[destid][0]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[cmd][0]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][74]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][73]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][72]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][71]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][70]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][69]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][68]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][67]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][66]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][65]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][64]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][63]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][62]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][61]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][60]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][59]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][58]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][57]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][56]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][55]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][54]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][53]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][52]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][51]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][50]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][49]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][48]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][47]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][46]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][45]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][44]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][43]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][42]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][41]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][40]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][39]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][38]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][37]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][36]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][35]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][34]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][33]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][32]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][31]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][30]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][29]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][28]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][27]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][26]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][25]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][24]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][23]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][22]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][21]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][20]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][19]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][18]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][17]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][16]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][15]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][14]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][13]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][12]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][11]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][10]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][9]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][8]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][7]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][6]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][5]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][4]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][3]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][2]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][1]}]
set_load -pin_load 3 [get_ports {fsb_node_data_o[data][0]}]
set_max_transition 0.069 [get_ports rocc_cmd_v_o]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_funct][6]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_funct][5]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_funct][4]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_funct][3]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_funct][2]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_funct][1]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_funct][0]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_rs2][4]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_rs2][3]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_rs2][2]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_rs2][1]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_rs2][0]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_rs1][4]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_rs1][3]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_rs1][2]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_rs1][1]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_rs1][0]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_xd]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_xs1]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_xs2]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_rd][4]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_rd][3]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_rd][2]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_rd][1]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_rd][0]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_opcode][6]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_opcode][5]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_opcode][4]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_opcode][3]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_opcode][2]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_opcode][1]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[inst_opcode][0]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][63]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][62]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][61]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][60]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][59]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][58]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][57]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][56]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][55]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][54]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][53]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][52]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][51]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][50]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][49]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][48]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][47]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][46]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][45]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][44]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][43]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][42]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][41]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][40]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][39]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][38]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][37]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][36]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][35]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][34]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][33]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][32]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][31]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][30]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][29]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][28]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][27]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][26]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][25]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][24]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][23]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][22]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][21]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][20]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][19]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][18]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][17]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][16]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][15]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][14]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][13]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][12]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][11]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][10]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][9]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][8]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][7]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][6]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][5]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][4]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][3]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][2]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][1]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs1][0]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][63]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][62]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][61]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][60]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][59]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][58]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][57]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][56]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][55]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][54]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][53]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][52]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][51]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][50]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][49]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][48]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][47]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][46]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][45]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][44]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][43]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][42]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][41]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][40]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][39]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][38]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][37]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][36]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][35]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][34]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][33]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][32]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][31]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][30]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][29]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][28]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][27]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][26]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][25]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][24]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][23]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][22]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][21]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][20]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][19]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][18]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][17]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][16]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][15]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][14]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][13]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][12]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][11]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][10]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][9]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][8]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][7]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][6]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][5]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][4]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][3]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][2]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][1]}]
set_max_transition 0.069 [get_ports {rocc_cmd_data_o[rs2][0]}]
set_max_transition 0.069 [get_ports rocc_resp_ready_o]
set_max_transition 0.069 [get_ports rocc_mem_req_ready_o]
set_max_transition 0.069 [get_ports rocc_mem_resp_v_o]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][39]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][38]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][37]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][36]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][35]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][34]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][33]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][32]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][31]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][30]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][29]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][28]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][27]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][26]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][25]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][24]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][23]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][22]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][21]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][20]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][19]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][18]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][17]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][16]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][15]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][14]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][13]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][12]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][11]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][10]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][9]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][8]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][7]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][6]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][5]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][4]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][3]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][2]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][1]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[addr][0]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[tag][9]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[tag][8]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[tag][7]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[tag][6]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[tag][5]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[tag][4]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[tag][3]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[tag][2]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[tag][1]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[tag][0]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[cmd][4]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[cmd][3]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[cmd][2]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[cmd][1]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[cmd][0]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[typ][2]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[typ][1]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[typ][0]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][63]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][62]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][61]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][60]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][59]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][58]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][57]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][56]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][55]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][54]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][53]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][52]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][51]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][50]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][49]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][48]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][47]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][46]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][45]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][44]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][43]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][42]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][41]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][40]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][39]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][38]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][37]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][36]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][35]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][34]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][33]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][32]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][31]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][30]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][29]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][28]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][27]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][26]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][25]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][24]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][23]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][22]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][21]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][20]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][19]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][18]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][17]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][16]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][15]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][14]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][13]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][12]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][11]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][10]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][9]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][8]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][7]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][6]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][5]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][4]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][3]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][2]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][1]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data][0]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[nack]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[replay]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[has_data]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][63]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][62]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][61]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][60]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][59]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][58]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][57]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][56]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][55]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][54]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][53]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][52]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][51]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][50]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][49]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][48]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][47]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][46]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][45]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][44]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][43]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][42]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][41]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][40]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][39]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][38]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][37]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][36]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][35]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][34]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][33]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][32]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][31]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][30]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][29]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][28]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][27]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][26]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][25]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][24]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][23]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][22]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][21]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][20]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][19]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][18]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][17]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][16]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][15]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][14]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][13]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][12]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][11]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][10]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][9]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][8]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][7]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][6]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][5]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][4]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][3]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][2]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][1]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[data_word_bypass][0]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][63]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][62]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][61]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][60]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][59]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][58]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][57]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][56]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][55]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][54]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][53]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][52]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][51]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][50]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][49]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][48]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][47]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][46]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][45]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][44]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][43]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][42]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][41]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][40]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][39]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][38]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][37]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][36]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][35]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][34]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][33]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][32]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][31]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][30]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][29]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][28]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][27]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][26]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][25]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][24]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][23]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][22]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][21]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][20]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][19]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][18]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][17]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][16]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][15]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][14]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][13]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][12]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][11]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][10]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][9]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][8]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][7]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][6]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][5]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][4]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][3]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][2]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][1]}]
set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o[store_data][0]}]
set_max_transition 0.069 [get_ports {rocc_ctrl_o[s]}]
set_max_transition 0.069 [get_ports {rocc_ctrl_o[exception]}]
set_max_transition 0.069 [get_ports {rocc_ctrl_o[host_id]}]
set_max_transition 0.069 [get_ports fsb_node_ready_o]
set_max_transition 0.069 [get_ports fsb_node_v_o]
set_max_transition 0.069 [get_ports {fsb_node_data_o[destid][3]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[destid][2]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[destid][1]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[destid][0]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[cmd][0]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][74]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][73]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][72]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][71]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][70]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][69]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][68]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][67]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][66]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][65]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][64]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][63]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][62]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][61]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][60]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][59]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][58]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][57]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][56]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][55]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][54]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][53]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][52]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][51]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][50]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][49]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][48]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][47]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][46]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][45]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][44]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][43]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][42]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][41]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][40]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][39]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][38]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][37]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][36]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][35]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][34]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][33]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][32]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][31]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][30]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][29]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][28]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][27]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][26]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][25]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][24]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][23]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][22]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][21]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][20]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][19]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][18]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][17]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][16]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][15]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][14]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][13]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][12]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][11]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][10]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][9]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][8]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][7]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][6]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][5]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][4]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][3]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][2]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][1]}]
set_max_transition 0.069 [get_ports {fsb_node_data_o[data][0]}]
create_clock [get_ports clk_i]  -name core_clk  -period 5  -waveform {0 2.5}
set_clock_latency -source 0  [get_clocks core_clk]
set_clock_uncertainty 0.03  [get_clocks core_clk]
set_clock_transition -min -fall 0.069 [get_clocks core_clk]
set_clock_transition -min -rise 0.069 [get_clocks core_clk]
set_clock_transition -max -fall 0.069 [get_clocks core_clk]
set_clock_transition -max -rise 0.069 [get_clocks core_clk]
set_false_path   -to [list [get_ports {rocc_ctrl_o[s]}] [get_ports {rocc_ctrl_o[exception]}] [get_ports {rocc_ctrl_o[host_id]}]]
set_input_delay -clock core_clk  2.51  [get_ports rocc_cmd_ready_i]
set_input_delay -clock core_clk  2.51  [get_ports rocc_resp_v_i]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[rd][4]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[rd][3]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[rd][2]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[rd][1]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[rd][0]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][63]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][62]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][61]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][60]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][59]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][58]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][57]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][56]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][55]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][54]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][53]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][52]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][51]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][50]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][49]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][48]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][47]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][46]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][45]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][44]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][43]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][42]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][41]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][40]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][39]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][38]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][37]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][36]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][35]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][34]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][33]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][32]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][31]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][30]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][29]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][28]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][27]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][26]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][25]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][24]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][23]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][22]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][21]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][20]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][19]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][18]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][17]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][16]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][15]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][14]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][13]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][12]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][11]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][10]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][9]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][8]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][7]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][6]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][5]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][4]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][3]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][2]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][1]}]
set_input_delay -clock core_clk  2.51  [get_ports {rocc_resp_data_i[data][0]}]
set_input_delay -clock core_clk  3.01  [get_ports rocc_mem_req_v_i]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[tag][9]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[tag][8]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[tag][7]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[tag][6]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[tag][5]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[tag][4]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[tag][3]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[tag][2]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[tag][1]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[tag][0]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[cmd][4]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[cmd][3]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[cmd][2]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[cmd][1]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[cmd][0]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[typ][2]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[typ][1]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[typ][0]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[phys]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][39]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][38]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][37]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][36]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][35]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][34]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][33]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][32]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][31]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][30]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][29]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][28]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][27]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][26]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][25]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][24]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][23]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][22]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][21]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][20]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][19]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][18]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][17]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][16]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][15]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][14]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][13]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][12]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][11]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][10]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][9]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][8]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][7]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][6]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][5]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][4]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][3]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][2]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][1]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[addr][0]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][63]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][62]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][61]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][60]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][59]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][58]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][57]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][56]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][55]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][54]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][53]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][52]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][51]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][50]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][49]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][48]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][47]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][46]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][45]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][44]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][43]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][42]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][41]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][40]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][39]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][38]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][37]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][36]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][35]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][34]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][33]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][32]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][31]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][30]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][29]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][28]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][27]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][26]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][25]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][24]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][23]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][22]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][21]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][20]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][19]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][18]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][17]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][16]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][15]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][14]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][13]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][12]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][11]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][10]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][9]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][8]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][7]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][6]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][5]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][4]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][3]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][2]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][1]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_mem_req_data_i[data][0]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_ctrl_i[busy]}]
set_input_delay -clock core_clk  2.76  [get_ports {rocc_ctrl_i[interrupt]}]
set_input_delay -clock core_clk  2.51  [get_ports fsb_node_v_i]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[destid][3]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[destid][2]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[destid][1]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[destid][0]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[cmd][0]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][74]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][73]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][72]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][71]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][70]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][69]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][68]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][67]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][66]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][65]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][64]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][63]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][62]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][61]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][60]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][59]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][58]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][57]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][56]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][55]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][54]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][53]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][52]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][51]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][50]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][49]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][48]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][47]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][46]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][45]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][44]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][43]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][42]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][41]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][40]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][39]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][38]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][37]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][36]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][35]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][34]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][33]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][32]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][31]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][30]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][29]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][28]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][27]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][26]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][25]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][24]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][23]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][22]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][21]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][20]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][19]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][18]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][17]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][16]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][15]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][14]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][13]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][12]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][11]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][10]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][9]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][8]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][7]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][6]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][5]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][4]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][3]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][2]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][1]}]
set_input_delay -clock core_clk  2.51  [get_ports {fsb_node_data_i[data][0]}]
set_input_delay -clock core_clk  3.01  [get_ports fsb_node_yumi_i]
set_input_delay -clock core_clk  2.51  [get_ports reset_i]
set_input_delay -clock core_clk  2.51  [get_ports en_i]
set_output_delay -clock core_clk  2.51  [get_ports rocc_cmd_v_o]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_funct][6]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_funct][5]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_funct][4]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_funct][3]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_funct][2]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_funct][1]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_funct][0]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_rs2][4]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_rs2][3]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_rs2][2]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_rs2][1]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_rs2][0]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_rs1][4]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_rs1][3]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_rs1][2]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_rs1][1]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_rs1][0]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_xd]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_xs1]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_xs2]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_rd][4]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_rd][3]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_rd][2]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_rd][1]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_rd][0]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_opcode][6]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_opcode][5]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_opcode][4]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_opcode][3]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_opcode][2]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_opcode][1]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[inst_opcode][0]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][63]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][62]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][61]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][60]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][59]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][58]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][57]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][56]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][55]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][54]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][53]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][52]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][51]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][50]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][49]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][48]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][47]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][46]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][45]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][44]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][43]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][42]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][41]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][40]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][39]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][38]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][37]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][36]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][35]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][34]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][33]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][32]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][31]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][30]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][29]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][28]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][27]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][26]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][25]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][24]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][23]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][22]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][21]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][20]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][19]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][18]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][17]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][16]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][15]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][14]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][13]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][12]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][11]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][10]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][9]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][8]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][7]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][6]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][5]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][4]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][3]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][2]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][1]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs1][0]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][63]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][62]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][61]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][60]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][59]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][58]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][57]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][56]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][55]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][54]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][53]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][52]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][51]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][50]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][49]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][48]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][47]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][46]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][45]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][44]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][43]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][42]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][41]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][40]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][39]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][38]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][37]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][36]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][35]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][34]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][33]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][32]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][31]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][30]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][29]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][28]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][27]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][26]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][25]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][24]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][23]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][22]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][21]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][20]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][19]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][18]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][17]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][16]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][15]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][14]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][13]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][12]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][11]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][10]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][9]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][8]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][7]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][6]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][5]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][4]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][3]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][2]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][1]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_cmd_data_o[rs2][0]}]
set_output_delay -clock core_clk  2.76  [get_ports rocc_mem_req_ready_o]
set_output_delay -clock core_clk  2.51  [get_ports rocc_mem_resp_v_o]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][39]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][38]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][37]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][36]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][35]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][34]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][33]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][32]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][31]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][30]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][29]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][28]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][27]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][26]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][25]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][24]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][23]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][22]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][21]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][20]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][19]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][18]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][17]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][16]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][15]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][14]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][13]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][12]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][11]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][10]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][9]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][8]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][7]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][6]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][5]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][4]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][3]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][2]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][1]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[addr][0]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[tag][9]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[tag][8]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[tag][7]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[tag][6]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[tag][5]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[tag][4]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[tag][3]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[tag][2]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[tag][1]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[tag][0]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[cmd][4]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[cmd][3]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[cmd][2]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[cmd][1]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[cmd][0]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[typ][2]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[typ][1]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[typ][0]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][63]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][62]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][61]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][60]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][59]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][58]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][57]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][56]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][55]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][54]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][53]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][52]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][51]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][50]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][49]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][48]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][47]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][46]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][45]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][44]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][43]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][42]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][41]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][40]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][39]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][38]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][37]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][36]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][35]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][34]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][33]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][32]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][31]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][30]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][29]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][28]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][27]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][26]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][25]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][24]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][23]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][22]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][21]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][20]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][19]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][18]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][17]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][16]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][15]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][14]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][13]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][12]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][11]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][10]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][9]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][8]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][7]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][6]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][5]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][4]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][3]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][2]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][1]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data][0]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[nack]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[replay]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[has_data]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][63]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][62]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][61]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][60]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][59]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][58]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][57]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][56]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][55]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][54]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][53]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][52]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][51]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][50]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][49]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][48]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][47]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][46]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][45]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][44]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][43]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][42]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][41]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][40]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][39]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][38]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][37]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][36]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][35]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][34]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][33]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][32]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][31]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][30]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][29]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][28]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][27]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][26]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][25]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][24]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][23]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][22]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][21]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][20]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][19]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][18]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][17]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][16]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][15]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][14]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][13]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][12]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][11]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][10]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][9]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][8]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][7]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][6]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][5]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][4]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][3]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][2]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][1]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[data_word_bypass][0]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][63]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][62]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][61]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][60]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][59]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][58]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][57]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][56]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][55]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][54]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][53]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][52]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][51]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][50]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][49]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][48]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][47]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][46]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][45]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][44]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][43]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][42]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][41]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][40]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][39]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][38]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][37]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][36]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][35]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][34]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][33]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][32]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][31]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][30]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][29]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][28]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][27]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][26]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][25]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][24]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][23]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][22]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][21]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][20]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][19]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][18]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][17]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][16]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][15]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][14]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][13]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][12]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][11]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][10]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][9]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][8]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][7]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][6]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][5]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][4]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][3]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][2]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][1]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_mem_resp_data_o[store_data][0]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_ctrl_o[s]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_ctrl_o[exception]}]
set_output_delay -clock core_clk  2.51  [get_ports {rocc_ctrl_o[host_id]}]
set_output_delay -clock core_clk  2.51  [get_ports rocc_resp_ready_o]
set_output_delay -clock core_clk  2.51  [get_ports fsb_node_ready_o]
set_output_delay -clock core_clk  3.01  [get_ports fsb_node_v_o]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[destid][3]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[destid][2]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[destid][1]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[destid][0]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[cmd][0]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][74]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][73]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][72]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][71]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][70]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][69]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][68]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][67]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][66]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][65]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][64]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][63]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][62]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][61]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][60]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][59]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][58]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][57]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][56]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][55]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][54]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][53]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][52]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][51]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][50]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][49]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][48]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][47]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][46]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][45]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][44]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][43]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][42]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][41]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][40]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][39]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][38]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][37]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][36]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][35]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][34]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][33]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][32]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][31]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][30]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][29]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][28]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][27]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][26]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][25]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][24]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][23]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][22]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][21]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][20]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][19]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][18]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][17]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][16]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][15]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][14]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][13]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][12]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][11]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][10]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][9]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][8]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][7]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][6]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][5]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][4]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][3]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][2]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][1]}]
set_output_delay -clock core_clk  2.51  [get_ports {fsb_node_data_o[data][0]}]
set_input_transition -max 0.069  [get_ports clk_i]
set_input_transition -min 0.069  [get_ports clk_i]
set_input_transition -max 0.069  [get_ports reset_i]
set_input_transition -min 0.069  [get_ports reset_i]
set_input_transition -max 0.069  [get_ports en_i]
set_input_transition -min 0.069  [get_ports en_i]
set_input_transition -max 0.069  [get_ports rocc_cmd_ready_i]
set_input_transition -min 0.069  [get_ports rocc_cmd_ready_i]
set_input_transition -max 0.069  [get_ports rocc_resp_v_i]
set_input_transition -min 0.069  [get_ports rocc_resp_v_i]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[rd][4]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[rd][4]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[rd][3]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[rd][3]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[rd][2]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[rd][2]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[rd][1]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[rd][1]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[rd][0]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[rd][0]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][63]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][63]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][62]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][62]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][61]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][61]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][60]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][60]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][59]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][59]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][58]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][58]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][57]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][57]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][56]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][56]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][55]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][55]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][54]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][54]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][53]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][53]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][52]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][52]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][51]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][51]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][50]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][50]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][49]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][49]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][48]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][48]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][47]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][47]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][46]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][46]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][45]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][45]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][44]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][44]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][43]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][43]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][42]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][42]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][41]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][41]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][40]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][40]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][39]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][39]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][38]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][38]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][37]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][37]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][36]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][36]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][35]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][35]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][34]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][34]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][33]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][33]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][32]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][32]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][31]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][31]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][30]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][30]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][29]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][29]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][28]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][28]}]
set_input_transition -max 0.069  [get_ports {rocc_resp_data_i[data][27]}]
set_input_transition -min 0.069  [get_ports {rocc_resp_data_i[data][27]}]
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set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][30]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][29]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][29]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][28]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][28]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][27]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][27]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][26]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][26]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][25]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][25]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][24]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][24]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][23]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][23]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][22]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][22]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][21]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][21]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][20]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][20]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][19]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][19]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][18]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][18]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][17]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][17]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][16]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][16]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][15]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][15]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][14]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][14]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][13]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][13]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][12]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][12]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][11]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][11]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][10]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][10]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][9]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][9]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][8]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][8]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][7]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][7]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][6]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][6]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][5]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][5]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][4]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][4]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][3]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][3]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][2]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][2]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][1]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][1]}]
set_input_transition -max 0.069  [get_ports {rocc_mem_req_data_i[data][0]}]
set_input_transition -min 0.069  [get_ports {rocc_mem_req_data_i[data][0]}]
set_input_transition -max 0.069  [get_ports {rocc_ctrl_i[busy]}]
set_input_transition -min 0.069  [get_ports {rocc_ctrl_i[busy]}]
set_input_transition -max 0.069  [get_ports {rocc_ctrl_i[interrupt]}]
set_input_transition -min 0.069  [get_ports {rocc_ctrl_i[interrupt]}]
set_input_transition -max 0.069  [get_ports fsb_node_v_i]
set_input_transition -min 0.069  [get_ports fsb_node_v_i]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[destid][3]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[destid][3]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[destid][2]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[destid][2]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[destid][1]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[destid][1]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[destid][0]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[destid][0]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[cmd][0]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[cmd][0]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][74]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][74]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][73]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][73]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][72]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][72]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][71]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][71]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][70]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][70]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][69]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][69]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][68]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][68]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][67]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][67]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][66]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][66]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][65]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][65]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][64]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][64]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][63]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][63]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][62]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][62]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][61]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][61]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][60]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][60]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][59]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][59]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][58]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][58]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][57]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][57]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][56]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][56]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][55]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][55]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][54]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][54]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][53]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][53]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][52]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][52]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][51]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][51]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][50]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][50]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][49]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][49]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][48]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][48]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][47]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][47]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][46]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][46]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][45]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][45]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][44]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][44]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][43]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][43]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][42]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][42]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][41]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][41]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][40]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][40]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][39]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][39]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][38]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][38]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][37]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][37]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][36]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][36]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][35]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][35]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][34]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][34]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][33]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][33]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][32]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][32]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][31]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][31]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][30]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][30]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][29]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][29]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][28]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][28]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][27]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][27]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][26]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][26]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][25]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][25]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][24]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][24]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][23]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][23]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][22]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][22]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][21]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][21]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][20]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][20]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][19]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][19]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][18]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][18]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][17]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][17]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][16]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][16]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][15]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][15]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][14]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][14]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][13]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][13]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][12]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][12]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][11]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][11]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][10]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][10]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][9]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][9]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][8]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][8]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][7]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][7]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][6]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][6]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][5]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][5]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][4]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][4]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][3]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][3]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][2]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][2]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][1]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][1]}]
set_input_transition -max 0.069  [get_ports {fsb_node_data_i[data][0]}]
set_input_transition -min 0.069  [get_ports {fsb_node_data_i[data][0]}]
set_input_transition -max 0.069  [get_ports fsb_node_yumi_i]
set_input_transition -min 0.069  [get_ports fsb_node_yumi_i]
